Monday, October 18, 2010

Carbon Microchips Accelerate Beyond Silicon

    Carbon Microchips Accelerate Beyond Silicon
  • Pioneering engineering efforts at Georgia Tech are bringing carbon microchips closer to commercialization by fabricating pure carbon sheets—graphene—into the world's largest carbon-transistor array.
  • Pioneering engineering efforts at Georgia Tech are bringing carbon microchips closer to commercialization by fabricating pure carbon sheets—graphene—into the world's largest carbon-transistor array.Researchers around the world are inventing ways to harness carbon—an organic material—to build smaller, faster microchips that sidestep the looming problems with inorganic silicon, which is becoming increasingly difficult to fabricate at the atomic level. IBM, for instance, recently demonstrated how to fabricate field-effect transistors (FETs) by smoothing out carbon into atomically thin sheets, called graphene.
    Now the Georgia Institute of Technology (Georgia Tech) has advanced graphene one more step by inventing a "templated growth" technique for fabricating what they claim is the world's largest array of organic carbon-based graphene transistors.
     Georgia Tech's new "templated growth" technique forces graphene sheets (black hexagons) to crystallize on contoured edges on a silicon carbide substrate (source: Georgia Tech).
    Semiconductor researchers worldwide agree that pure carbon sheets of graphene are destined to enable the super-fast, ultra-high-density microchips of the future, but techniques for realizing that dream are all over the map. So far, the conventional chemical vapor deposition (CVD) techniques universally used to fabricate all silicon chips today—from Intel's iCore to USB flash drives—have not worked for graphene unless restricted to substandard wafers just of around an inch in area, compared with the 12-inch wafers used today for silicon chips.

    Georgia Tech's technique, on the other hand, could potentially be used on any-size wafer. The technique works by using a template to trace the contours of the desired circuitry on silicon carbide (SiC) wafers, then boiling off the silicon—allowing the resulting pure carbon to grow into transistor arrays along those templated contours. The resulting perfect arrays of graphene transistors side-steps the problems that prevented using conventional chemical-vapor deposition of graphene, followed by patterning it into circuits, as is done for silicon chips.

    After the graphene transistor channel is grown, conventional lithography can add a insulating dielectric and gate on top with the source and drain electrodes (gold) at each end of the channel (source: Georgia Tech). 
    The new "templated growth" technique, pioneered in the lab of Georgia Tech Professor Walter de Heer, has the potential to enable entire 12-inch wafers to be fabricated by growing billions of graphene transistors in one fell swoop. To demonstrate the technique, de Heer's lab recently showed an array of 10,000 graphene FETs crammed into an area of just 0.24 square centimeters—the densest graphene transistor array ever created.
    Funding for the project came from the National Science Foundation, the W.M. Keck Foundation, and the Nanoelectronics Research Initiative Institute for Nanoelectronics Discovery and Exploration.

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